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eInfochips’ SPI VMM based VIP is highly configurable, reusable, scalable and extensible verification intellectual property that is suitable for verification of SPI Master/ Slave.

• Supports Master and Slave Mode
• Configurable clock polarity and clock phase
• Configurable baud rate
• Configurable shift register width
• Supports multi-slave system
• Support On interrupt transfer configurability for single slave application only (application point of view)
• Support wait mode, with immediate stop. (application point of view)
• Highly flexible and configurable
• Supports various error injection and detection
• Built in SPI bus monitor provides extensive protocol checking
• Provides verification scalability using functional coverage
• Provides hook-up at various stages of BFM for user interference
• Provides UL (Upper Layer) connectivity through channel, to allow user to use external generator
• Provides received data logging facility for UL, to provide received data (transaction) to UL using channel
• Uses open source VMM-1.1

Semiconductors (29)