AVM 3.0 & OVM Class based AMBA AHB SystemVerilog Verification Component

The widely adopted AHB System Bus connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory and interfaces. AHB is a new generation of AMBA bus intended to address the requirements of high-performance synthesizable designs.

eInfochipsí AMBA AHB OVM Class based Verification Component is based on reusable methodology that allows coverage driven verification suitable for verifying Master, Slave and AHB bus with various combinations as the DUT.

AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB OVM Class based VIP is a readymade highly configurable SystemVerilog Verification Component suitable for verification of AMBA AHB master and slave DUT. The AHB SV VIP provides all necessary building blocks to easily test master/slave DUT with the AHB protocol. The OVM Class based Verification Component can be easily configured and integrated with the verification environment.

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