eVCs are reusable Verification Components that can be used to establish ready-made verification environment. Each eVC is capable of acting as full verification environment or as a plug-in to an existing environment.

eInfochips' eVCs are designed for verification of today's SoC designs. With their object-oriented architecture, eInfochips' eVCs are building blocks for establishing complex and comprehensive verification environment in very short time.

The SPI 4 interface is used for packet / cell transfer between physical layer and link layer devices for applications concerning aggregate bandwidth of OC-192 ATM , Packet over SONET/SDH and 10 Gb/s Ethernet. SPI 4 P2 eVC represents the data link layer. It can be used to verify physical layer and data link layer devices that follow the SPI 4 P2 protocol. The eVC consists of Packet Generator, Packet Analyzer, Functional Checker and Functional Coverage modules. It can work in both Verilog & VHDL environments and with HDL simulators that are supported by Specman.

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